1. Field of the Invention
This invention relates to architecture of integrated circuits. More particularly, it relates to the layout design for filling open areas on each metal layer of an integrated circuit (IC).
2. Background of Related Art
One process in the manufacture of integrated circuits is referred to as an oxide chemical-mechanical polishing (CMP) process. CMP is very effective at reducing the as-deposited height, and achieves a measure of global planarization not possible with either spin-on or resist etchback techniques. However, CMP processes are hampered by layout pattern sensitivities which cause certain regions on a chip to have thicker dielectric layers than other regions due to differences in underlying topology.
Layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. Various process choices have been attempted by those in the art, with little appreciable variation in pattern-dependent dielectric thickness. Thus, the only viable choice available for reducing layout pattern dependent dielectric thickness variation is to change the layout pattern itself via the introduction of metal fill patterning.
Metal fill patterning is a process for filling large open areas on each metal layer with a metal fill pattern to provide a suitable metal density appropriate for relevant foundry technologies. Conventionally, the elements of the metal fill pattern are either grounded, or left floating, to compensate for pattern-driven variations. One conventional design utilizes a metal fill design rule that requires that all blank areas greater than 1 mm×1 mm in size have a metal fill pattern with an optimal density of 50%.
Conventional metal fill structures are either electrically grounded, or left electrically floating, or isolated. Grounded metal fill patterns tend to affect delay attributes in a layout, while floating or isolated metal fill patterns tend to increase coupling/crosstalk attributes.
Conventionally, metal-fill patterns are often produced en masse after chip level routing is complete. However, the inventors of the present application have appreciated that this is a problem, particularly for analog circuits which may be sensitive to the placement of these structures (for matching and other reasons). For example, conventional techniques place the structure of metal fill patterns deterministically, before the cell is placed, to avoid final, random placement.
One example of a conventional metal fill pattern is shown in FIG. 5, which shows a vertical line metal fill pattern 200 as disclosed by Stine et al. in “The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes”, IEEE Transactions on Electron Devices, Vol. 45, No. 3, March 1998. In the example of FIG. 5, the vertical lines 202 of the metal fill pattern 200 are all commonly grounded.
Stine et al. also disclose a floating block metal fill pattern 300, as depicted in FIG. 6 herein.
Yet another example of a conventional deterministic approach is the use of so-called waffle-grid metal fill pattern 400, as shown in FIG. 7.
As shown in FIG. 7, a metal mesh or waffle-grid shaped metal fill pattern 400 is either electrically floated or grounded in an attempt to improve delay and/or crosstalk parameters.
While conventional techniques improve upon prior techniques, there is room for additional improvement. For instance, in conventional techniques the metal fill pattern functions solely as metal fill, with little or no significant other function. There is a need for a better metal fill pattern technique to better improve delay and/or crosstalk parameters, as well as producing better utilization of available space with metal fill patterns.